1. Field of the Invention
This invention relates to the transfer of information in computer systems. Specifically, this invention relates to a novel system and method that enhances overall computer system performance by implementing a secondary bus infrastructure to avoid data phase transaction latencies during information transfers.
2. Description of Related Art and General Background
As indicated in FIG. 1, conventional computer system 100 comprises a host adapter 105 and a plurality of media adapters 175A-175U. The number of media adapters 175A-175U may be limited by system 100 configuration and system bus infrastructure 150 (e.g., 21 adapters for PCI configuration). Host adapter 105 includes processor 110 and memory 120. Processor 110 may comprise one or more microprocessors, for example, and includes system controller functionality to supervise and control the various components of system 100. Memory 120 may comprise semiconductor memory, such as, read-only memory (ROM) and/or random-access memory (RAM), arranged in one or more hierarchical levels (e.g. Level-1 cache, Level-2 cache, main memory, Basic Input/Output System (BIOS), etc.).
System 100 supports the input of information from, and/or the output of information to, one or more peripheral media devices 180A-180U through media controllers 170A-170U. Examples of such devices 180A-180U include video displays, keyboards, printers, devices for input and/or output of audio and video, network interfaces, and secondary storage media (i.e., disk drives, tape drives), etc. Such media devices 180A-180U may be coupled to media adapters 175A-175U, via media controllers 170A-170U, which communicate with processor 110 and/or memory 120 via system bus infrastructure 150. System bus 150 may be configured as a Peripheral Connect Interface (PCI) bus, as defined by PCI Bus Specification, Rev. 2.2, PCI Special Interest Group, Hillsboro, Oreg.
PCI is a high-speed interconnection system that accommodates data transfer between processor 110, host adapter 105 components, and media adapter 175i components. As indicated in FIG. 1, data transfers are conveyed over system bus 150 (e.g., PCI bus 150), which defines a connection path between a host PCI controller 140 and a media PCI controller 160i. Host PCI controller 140 and media PCI controller 160i serve to isolate system bus 150 from the host local bus 125 and media local bus 165i. Moreover, PCI may incorporate Direct Memory Access (DMA) functionality to accommodate the data transfer between a media device 180i to the host adapter memory 120, in order to free processor 110 from data transfer involvement and speed up overall computer performance. PCI implements DMA by utilizing bus-mastering techniques to delegate input/output (I/O) control to host PCI controller 140 and media PCI controller 160i. 
PCI is capable of transmitting both, address and data signals, 32 bits or 64 bits at a time across the connection path. For example, the transfer of information may be initiated as a single data phase transaction, in which a read or write address is transmitted over one clock cycle and a corresponding data unit is transmitted over a subsequent cycle. Alternatively, transfers may be initiated as a multiple (i.e., xe2x80x9cburstyxe2x80x9d) data phase transactions, in which the read or write address is transmitted over one clock cycle and a plurality of data units is transmitted over a predetermined number of successive cycles. Because of the use of one address per multiple data units, multiple data phase transactions provide a more efficient use of the PCI bus 150 bandwidth than single data phase transactions. It is important to note that, when targeted for a data transaction, each media adapter 175i may possess a different delay based on the manner in which they respond to data requests. In other words, each media adapter 175i may require the passage of a predetermined number of clock cycles (e.g., up to 16 clock cycles) between the address clock cycle and the subsequent initial data cycle during a target read. This passage of predetermined clock cycles germane to each media adapter 175i is referred to xe2x80x9cinitial data phase latencyxe2x80x9d.
During normal information transfers between media adapters 175A-115U, transfers are typically conveyed over system bus 150 and are initiated as multiple data phase transactions, where initial data phase latencies comprise a negligible portion of the entire transaction interval. Media adapters 175A-175U may also require maintenance/message information transfers, performed as single data phase transactions, in which processor 110 accesses maintenance/messaging information from media controller 170i to ascertain and/or provide local configuration, command, management, and status information. Because, as noted above, single data phase transactions only transfer one data unit per clock cycle and because different media adapters 175A-175U may respond slower than others, single data phase transactions are particularly susceptible to the effects of initial data phase latencies. As such, the mixture of single data phase transactions and multiple data phase transactions over the same system bus 150, can have a deleterious effect on system performance (e.g., reducing theoretical system bus performance from 132 MBps to 13.2 MBps on a 32-bit PCI bus, assuming 10 single data phase maintenance/management transactions for every 1500 byte media adapter DMA data transfer). Therefore, what is needed is a system and method that avoids such data phase transaction latencies during information transfers to improve overall computer system performance.